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#	Item
761	Multi-threaded Performance Pitfalls 1 Multi-threaded Performance Pitfalls Ciaran McHale Add to Reading List Source URL: www.ciaranmchale.com Language: English - Date: 2008-05-17 08:17:25 Central processing unit Microprocessors Parallel computing Computer memory Threads Scalability Multi-core processor CPU cache Cache Computing Concurrent computing Computer hardware
762	Microsoft Word - Arch_WhitePaperB2 _2__6_12_09.doc Add to Reading List Source URL: www.chipwrights.com Language: English - Date: 2009-10-01 18:55:24 Electronic engineering Datapath Register file Instruction set ARM architecture Accumulator Processor register Memory address No instruction set computing Computer architecture Central processing unit Computer hardware
763	THE UNIVERSITY OF HONG KONG LABORATORY ANIMAL UNIT Animal Strains The following animal strains are currently held in the SPF (Specific Pathogen Free) Central Breeding Area of the LAU: Strain Add to Reading List Source URL: www.lau.hku.hk Language: English - Date: 2015-01-21 03:10:49 Harlan BALB/c House mouse C57 Albinism Dawley Sprague Albino Model organisms Biology Laboratory rat
764	Learning Bayesian Networks for Improved Instruction Cache Analysis Mark Bartlett, Iain Bate and James Cussens Department of Computer Science University of York Heslington, York, UK Add to Reading List Source URL: www.cs.york.ac.uk Language: English - Date: 2012-05-02 15:17:24 Computer hardware Computer architecture Central processing unit Bayesian network Networks CPU cache Worst-case execution time Graphical model Cache Statistics Bayesian statistics Statistical models
765	C8051F120C8051F130Mixed Signal ISP Flash MCU Family Analog Peripherals - 10 or 12-bit SAR ADC Add to Reading List Source URL: gdansk.bradley.edu Language: English - Date: 2015-02-19 03:04:54 Computer architecture Integrated circuits IBM PC compatibles Central processing unit Intel MCS-51 I²C Universal asynchronous receiver/transmitter Serial Peripheral Interface Bus TI MSP430 Microcontrollers Electronics Electronic engineering
766	Results of Water Level Measurement at Sub-drain Pits around Central Radioactive Waste Treatment Facility (Oct. 1 - Oct. 31, Unit: mm) Number Add to Reading List Source URL: www4.tepco.co.jp Language: English - Date: 2013-12-09 04:52:08 Chemistry Chemical engineering Incineration Thermal treatment Radioactive waste Waste Waste management Environment
767	ARM 7TDMI Data Sheet Issued: August 1995 Copyright Advanced RISC Machines Ltd (ARMAll rights reserved Add to Reading List Source URL: www.ndsretro.com Language: English - Date: 2006-12-01 15:44:11 Central processing unit Instruction set architectures ARM architecture Embedded systems ARM7 Instruction set Joint Test Action Group Reduced instruction set computing Microprocessor Computer architecture Computer hardware Electronic engineering
768	August 16, 2013 Tokyo Electric Power Company Results of Water Level Measurement at Sub-drain Pits around Central Radioactive Waste Treatment Facility (AprDec 31, Unit: mm) Add to Reading List Source URL: www4.tepco.co.jp Language: English - Date: 2013-09-11 02:51:32 LMS Jubilee Class River class frigate Rail transport Land transport Rolling stock
769	Results of Water Level Measurement at Sub-drain Pits around Central Radioactive Waste Treatment Facility (Nov. 1 - Nov. 30, Unit: mm) Number Add to Reading List Source URL: www4.tepco.co.jp Language: English - Date: 2013-12-09 00:30:44
770	Prefetching and Cache Management Using Task Lifetimes Vassilis Papaefstathiou∗ Manolis G.H. Katevenis∗ FORTH-ICS Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2014-02-26 04:38:59 Computer memory Cache Central processing unit Microprocessors CPU cache Prefetcher Multi-core processor Microarchitecture X86 Computer hardware Computing Computer architecture

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